The present invention relates to a sense amplifier circuit for a semiconductor memory device.
Shown in FIG. 4 is one type of a conventional sense amplifier circuit as applied to a semiconductor memory, for example, a mask ROM (read-only memory). This sense amplifier circuit includes a current mirror type differential amplifier circuit 10, a reference line REF connected to a power supply through a pMOS (p-channel metal oxide semiconductor) transistor Qp2, an on-state n-MOS transistor Qn5, a dummy bit line DBL connected to the reference line REF through the nMOS transistor Qn5, and dummy memory cell transistors Qn2 and Qn3 serially connected between the dummy bit line DBL and ground. Symmetrical to the reference line REF side are a data line DL connected to the power supply through a pMOS transistor Qp1, an nMOS transistor Qn4 which is switched by a column selection signal Cse1, and a bit line BL connected to the data line DL through the nMOS transistor Qn4. Multiple nMOS detected memory cell transistors Qn1 (only one transistor is shown in the figure for simplicity) are connected between the bit line BL and the ground.
The current mirror type differential amplifier circuit 10 includes a pair of pMOS transistors Qp3 and Qp4 connected to the power supply and having identical characteristics, a pair of nMOS transistors Qn6 and Qn7 serially connected to the Qp3 and Qp4 transistors, respectively, and likewise having identical characteristics, and an nMOS transistor Qn8 connected between the ground and the contacts of the transistors Qn6 and Qn7. The gates of the nMOS transistors Qn6 and Qn7 are connected, respectively, to the reference line REF and the data line DL. The detected memory cell transistor Qn1 is turned ON when a voltage is applied to the gate over the word line WL when in a logic state of "1", i.e., a low threshold value, as occurs with a normal enhancement transistor, and is in an OFF state in which virtually no current passes when in a "0" logic state, i.e., a high threshold value state. The nMOS dummy memory cell transistors Qn2 and Qn3 both have the same characteristics as the detected memory cell transistor Qn1 when in a "1" logic state.
The charge current which flows to the reference line REF from the power supply (potential Vcc) through the pMOS transistor Qp2 decreases as the potential Vref (hereinafter after the reference potential) of the reference line REF increases as shown by the dotted line 13 in FIG. 3. On the other hand, the discharge current which flows to the ground through the dummy memory cell transistors Qn2 and Qn3 from the reference line REF increases as the reference potential Vref increases as shown by the dot-dash line 14 in the same figure. Therefore, the reference potential Vref is determined by the balance between the discharge and charge currents mentioned above, becoming the potential Vc expressed by the intersection C of the dotted line 13 and the dot-dash line 14.
Furthermore, the charge current flowing from the power supply through the pMOS transistor Qp1 to the data line DL similarly decreases as the potential Vd1 (hereinafter the data line potential) of the data line DL increases as shown by the dotted line 13 in FIG. 3. When the detected memory cell transistor Qn1 is in a "1" logic state and the data line potential Vd1 rises, the discharge current discharged to the ground from the data line DL increases as indicated by the solid line 11. When the detected memory cell transistor Qn1 is in a "0" logic state, the discharge current remains flat at approximately zero as indicated by solid line 12 regardless of the value of the data line potential Vd1. Note that the discharge current 14 of the reference line REF becomes approximately one-half of the discharge current 11 of the data line DL due to the serial resistance of the dummy memory cell transistors Qn2 and Qn3.
When the logic state of the detected memory cell transistor Qn1 is "1", the data line potential Vd1 becomes the potential Va (&lt;Vc) indicated by the intersection A of the dotted line 13 and the solid line 11 due to the balance between the charge and discharge currents. Conversely, when the logic state of the memory cell transistor Qn1 is "0", the data line potential Vd1 becomes potential Vb (&gt;Vc) expressed by the intersection B of the dotted line 13 and the solid line 12. When the logic state of the detected memory cell transistor Qn1 is "1", the current mirror type differential amplifier circuit 10 receives the reference potential Vref=Vc and the data line potential Vd1=Va at the gates of the nMOS transistor Qn6 and Qn7, respectively, differentially amplifies the potentials, and sets the potential Vsa to a high level for output based on this potential difference. When the logic state of the detected memory cell transistor Qn1 is "0", the current mirror type differential amplifier circuit 10 receives the reference potential Vref=Vc and the data line potential Vd1=Vb at the gates of the nMOS transistor Qn6 and Qn7, respectively, differentially amplifies the potentials, and sets the potential Vsa to a low level for output. The logic state of the detected memory cell transistor Qn1 is thus detected.
The detected memory cell transistor Qn1 is designed so that the discharge current of the data line DL is approximately zero as shown by the solid line 12 in FIG. 3, when the logic state of the detected memory cell transistor Qn1 is "0". Due to variations introduced during manufacture, however, discharge currents which are too high to be ignored occasionally flow. This causes the value of the data line potential Vd1 to drop to a value less than the potential Vb, resulting in a difference with the reference potential Vref less than the design value ((Vb-Va)/2). As a result, a conventional sense amplifier circuit has nominal operational tolerance and presents stability problems. In extreme cases, an operating error occurs where the voltage relation becomes Vd1&lt;Vref (=Vc) though the logic state of the detected memory cell transistor Qn1 is "0".
In addition, the same problem occurs in the case of an EPROM or EEPROM sense amplifier circuit due to deterioration of the "0" state characteristics of the detected memory cell transistor accompanying rewriting of the detected memory cell.